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Global System in Package (SIP) Market Report 2014-2020
The rapid expansion of the System in Package (SiP) market has inspired research and development in System in Package (SiP) associated technology by Integrated Device Manufacturers (IDM) as well as Electronic Manufacturing Services (EMS) providers and Semiconductor Assembly Services (SAS). With this evolution of System in Package (SiP) technology during the last few decades, the future trend for System in Package (SiP) technology in the next decade or two will be clearer if we look at the future electronics market sectors such as mobile products, high-end computers, automobiles, flat-panel High-Definition TVs (HDTVs), and sensors for security, health care, and environment. The consumer mobile products will advance to more multi functionality, thus, realizing the digital convergent dream with flexible displays with LED as a light source, thin film, or nano batteries.
System on Package (SOP) is an emerging trend in the system miniaturization technology in divergence to System-on-Chip (SOC) at IC level and System in Package (SiP) at module level. System in Package (SiP) is obtained by thinning ICs from its original 800 micron thick wafer dimensions to 50 microns and stacking as many as 10 of these, one on top of the other, in 3D form. These are then interconnected by either wire bond or flip-chip technology. The current Through Silicon via (TSV) developments have further condensed System in Package (SiP) by replacing flip chip with pad to pad bonding.
The capability to integrate different technologies and to reduce total production cost and time to market are the prime drivers for System in Package (SiP) packaging. System in Package (SiP) has enabled the rapid integration of active and passive devices into single package solutions. This approach has also reduced product costs, allowing systems to be partitioned into the most cost-effective blocks. The stacked System in Package (SiP) alignments reduce the system size and eliminate the cost of individual packages for each die. They also improve signal transmission times and reduced power by minimizing capacitive loads between ICs.
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